Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102,400 nodes

Minor-embedding heuristics have become an indispensable tool for compiling problems in quadratically unconstrained binary optimization (QUBO) into the hardware graphs of quantum and CMOS annealing processors. While recent embedding been developed annealers moderate size (about 2000 nodes), latest processor (with 102,400 nodes) poses entirely new demands on heuristic. This raises question, if can maintain meaningful performance increasing size. Here, we develop improved version probabilistic-swap-shift-annealing (PSSA) heuristic [which has recently demonstrated to outperform standard by D-Wave Systems (Cai et al. http://arxiv.org/abs/1406.2741 , 2014)] evaluate its For random cubic Barábasi–Albert find PSSA consistently exceed threshold best known complete graph a factor 3.2 2.8, respectively, up with nodes. On other hand, constant edge density not even overcome deterministic guaranteed existence embedding. Finally, prove upper bound maximal embeddable show that currently optimal order fixed coordination number.